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ʽ�\I�@s�dZddlZddlmZmZmZmZmZmZddl	m
Z
mZmZm
Z
mZmZmZmZmZdddgZGdd�de�ZGd	d�de�ZGd
d�de�ZdS)z�
    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-2019 by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
�N)�
RegexLexer�bygroups�include�using�this�words)	�Text�Comment�Operator�Keyword�Name�String�Number�Punctuation�Error�VerilogLexer�SystemVerilogLexer�	VhdlLexerc@s�eZdZdZdZddgZdgZdgZdZde	j
dfd	efd
efdefde	jfd
e	j
fdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefdefdejfdeeeje�fdeeeje�d fed!d"d#�efed$d%d"d&�e	j
fed'd(d"d&�ejfed)d"d#�ej fd*ej!fd+efgd,ed-fd.ej"fd/efdefd0efgd1e	j
fd2e	j
fd3e	jd-fd4e	j
fd5e	j
fd	e	j
d-fgd6ejd-fgd7�Z#d8d9�Z$d:S);rzZ
    For verilog source code with preprocessor directives.

    .. versionadded:: 1.4
    Zverilog�vz*.vztext/x-verilogz(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`define�macroz\nz\s+z\\\nz/(\\\n)?/(\n|(.|\n)*?[^\\]\n)z/(\\\n)?[*](.|\n)*?[*](\\\n)?/z[{}#@]zL?"�stringz4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'z%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?z(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?z\*/z[~!%^&*+=|?:<>/-]z
[()\[\],.;\']z
`[a-zA-Z_]\w*z^(\s*)(package)(\s+)z^(\s*)(import)(\s+)�import)q�always�always_comb�	always_ff�always_latch�and�assign�	automatic�begin�break�buf�bufif0�bufif1�case�casex�casez�cmos�const�continue�deassign�default�defparam�disable�do�edge�else�end�endcase�endfunction�endgenerate�	endmodule�
endpackage�endprimitive�
endspecify�endtable�endtask�enum�event�final�for�force�forever�fork�function�generate�genvar�highz0�highz1�if�initial�inout�input�integer�join�large�
localparam�macromodule�medium�module�nand�negedge�nmos�nor�not�notif0�notif1�or�output�packed�	parameter�pmos�posedge�	primitive�pull0�pull1�pulldown�pullup�rcmos�ref�release�repeat�return�rnmos�rpmos�rtran�rtranif0�rtranif1�scalared�signed�small�specify�	specparamZstrengthr�strong0�strong1�struct�table�task�tran�tranif0�tranif1�type�typedef�unsigned�var�vectored�void�wait�weak0�weak1�while�xnor�xorz\b)�suffix)Z
accelerateZautoexpand_vectornetsZ
celldefineZdefault_nettyper0�elsifZ
endcelldefineZendifZ
endprotectZendprotectedZexpand_vectornetsZifdefZifndefrZnoaccelerateZnoexpand_vectornetsZnoremove_gatenamesZnoremove_netnamesZnounconnected_driveZprotect�	protectedZremove_gatenamesZremove_netnamesZresetallZ	timescaleZunconnected_driveZundef�`)�prefixr�)4�bitsZ
bitstorealZbitstoshortrealZcountdriversZdisplayZfcloseZfdisplayZfinish�floorZfmonitorZfopenZfstrobeZfwriteZ
getpattern�historyZincsaverJZitor�key�list�logZmonitorZ
monitoroffZ	monitoronZnokeyZnologZprinttimescale�randomZreadmembZreadmemh�realtimeZ
realtobits�resetZreset_countZreset_valueZrestartZrtoiZsaveZscaleZscopeZshortrealtobitsZ
showscopesZ
showvariablesZshowvarsZ	sreadmembZ	sreadmemhZstime�stopZstrobe�timeZ
timeformat�writez\$)�byte�shortint�int�longintrKr��bit�logic�reg�supply0�supply1�tri�triand�trior�tri0�tri1�trireg�uwire�wire�wand�woshortreal�realr�z[a-zA-Z_]\w*:(?!:)z\$?[a-zA-Z_]\w*�"z#popz/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})z	[^\\"\n]+z\\z[^/\n]+z/[*](.|\n)*?[*]/z//.*?\n�/z	(?<=\\)\nz	[\w:]+\*?)�rootrrrccsBx<t�||�D],\}}}|tkr.|��r.tj}|||fVqWdS)N)r�get_tokens_unprocessedr�isupper�Constant)�self�text�index�token�value�r��D/opt/alt/python37/lib/python3.7/site-packages/pygments/lexers/hdl.pyr��sz#VerilogLexer.get_tokens_unprocessedN)%�__name__�
__module__�__qualname__�__doc__�name�aliases�	filenames�	mimetypes�_wsr	�Preprocr�Single�	Multilinerr
�Charr�Float�Hex�Bin�Integer�Octrr
rr�rr�	Namespacer�Builtin�Type�Label�Escape�tokensr�r�r�r�r�rsz

c@s�eZdZdZdZddgZddgZdgZdZde	j
d	fd
eee
je�fdeee
je�dfd
efdefdefde	jfde	jfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefd efd!ejfed"d#d$�e
fed%d#d$�e	j
fed&d#d$�ejfd'ee
e�d(fed)d#d$�e
j fd*ej!fd+efgd,ej"d-fgd.ed-fd/ej#fd0efdefd1efgd2e	j
fd3e	jfd4e	jd-fd5e	j
fd6e	j
fd
e	j
d-fgd7ejd-fgd8�Z$d9d:�Z%d;S)<rz�
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.

    .. versionadded:: 1.5
    Z
systemverilog�svz*.svz*.svhztext/x-systemverilogz(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`definerz^(\s*)(package)(\s+)z^(\s*)(import)(\s+)rz\nz\s+z\\\nz/(\\\n)?/(\n|(.|\n)*?[^\\]\n)z/(\\\n)?[*](.|\n)*?[*](\\\n)?/z[{}#@]zL?"rz4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'z%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?z(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?z\*/z[~!%^&*+=|?:<>/-]z
[()\[\],.;\']z
`[a-zA-Z_]\w*)�Z	accept_on�aliasrrrrr�assertrZassumer�beforer�bindZbinsZbinsofr�r r!r"r#r�r$r%r&�cellZchandleZchecker�classZclockingr'�configr(Z
constraint�contextr)ZcoverZ
covergroupZ
coverpointZcrossr*r+r,Zdesignr-�distr.r/r0r1r2Z
endcheckerZendclassZendclockingZ	endconfigr3r4ZendgroupZendinterfacer5r6r7Z
endprogramZendpropertyZendsequencer8r9r:r;r<Z
eventuallyZexpectZexportZextends�externr=Zfirst_matchr>r?Zforeachr@rAZforkjoinrBrCrD�globalrErFrGZiffZifnoneZignore_binsZillegal_binsZimpliesr�incdirrrHrIrJZinside�instancer�rKZ	interfaceZ	intersectrLZjoin_anyZ	join_nonerMZletZliblist�library�localrNr�r�rO�matchesrPZmodportrQrRrS�newZnexttimerTrUZnoshowcancelledrVrWrX�nullrYrZ�packager[r\r]r^r_�priority�program�propertyr�r`rarbrcZpulsestyle_ondetectZpulsestyle_onevent�pureZrandZrandcZrandcaseZrandsequencerdr�r�rer�Z	reject_onrfrgZrestrictrhrirjrkrlrmZs_alwaysZs_eventuallyZ
s_nexttimeZs_untilZs_until_withrn�sequencer�Z	shortrealZ
showcancelledrorpZsolverqrr�staticrZstrongrsrtru�superr�r�Zsync_accept_onZsync_reject_onrvZtaggedrwrZ
throughoutr�Z
timeprecisionZtimeunitrxryrzr�r�r�r�r�r�r{r|�union�uniqueZunique0r}�untilZ
until_withZuntyped�user�r~rZvirtualr�r�Z
wait_orderr�Zweakr�r�r�Zwildcardr��withZwithinZworr�r�z\b)r�)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz
`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)Lz$displayz	$displaybz	$displayhz	$displayoz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz
$dumpportsallz$dumpportsflushz$dumpportslimitz
$dumpportsoffz$dumpportsonz	$dumpvarsz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz$finishz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz	$plusargsz$randomz	$readmembz	$readmemhz$rewindz$sformatz	$sformatfz$sscanfz$strobez$strobebz$strobehz$strobeoz$swritez$swritebz$swritehz$swriteoz$testz$ungetcz$value$plusargsz$writez$writebz$writehz
$writemembz
$writememhz$writeoz(class)(\s+)�	classname)r�r�r�r�rKr�r�r�r�r�r�r�r�r�r�r�r�r�r�r�r�r�r�z[a-zA-Z_]\w*:(?!:)z\$?[a-zA-Z_]\w*z[a-zA-Z_]\w*z#popr�z/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})z	[^\\"\n]+z\\z[^/\n]+z/[*](.|\n)*?[*]/z//.*?\nr�z	(?<=\\)\nz	[\w:]+\*?)r�r�rrrccsBx<t�||�D],\}}}|tkr.|��r.tj}|||fVqWdS)N)rr�rr�r�)r�r�r�r�r�r�r�r�r�sz)SystemVerilogLexer.get_tokens_unprocessedN)&r�r�r�r�r�r�r�r�r�r	r�rrrr�r�r�rr
r�rr�r�r�r�r�rr
rr�rr�r�r��Classr�r�r�r�r�r�r�r�s|


c@s�eZdZdZdZdgZddgZdgZej	ej
BZdefdefdefd	e
jfd
ejfdefdejfd
efdefdeeeej�fdeeee�fdeeeeje�fdeeeej�fdeejej�feddd�ejfdeeeej�fdeeeejeeeejee�	fdeejeee�fdeee�e�dfed�ed�ed�defged�dejfd efd!ed"fged#dd�ejfged$dd�efgd%ejfd&ejfd'ej fd(ej!fd)ej"fd*ej#fgd+�Z$d,S)-rz:
    For VHDL source code.

    .. versionadded:: 1.5
    Zvhdlz*.vhdlz*.vhdztext/x-vhdlz\nz\s+z\\\nz--.*?$z'(U|X|0|1|Z|W|L|H|-)'z[~!%^&*+=|?:<>/-]z
'[a-z_]\w*z
[()\[\],.;\']z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))ZstdZieeeZworkz\b)r�z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)�endblock�types�keywords�numbersz	[a-z_]\w*z(\s+)�;z#pop)Zbooleanr��	characterZseverity_levelrKr�Zdelay_lengthZnaturalZpositiverZ
bit_vectorZfile_open_kindZfile_open_statusZ
std_ulogicZstd_ulogic_vectorZ	std_logicZstd_logic_vectorror})_�abs�access�afterr��allr�architecture�arrayr��	attributer�block�body�bufferZbusr$Z	componentZ
configurationZconstantZ
disconnectZdowntor0r�r1�entity�exit�filer>rBrCZgeneric�groupZguardedrGZimpure�inZinertialrI�is�labelr��linkage�literalZloop�map�modrRr��nextrUrVr�Zof�on�openrYZothers�outr��portZ	postponedZ	procedure�processr��range�record�registerZreject�remrhZrolZror�selectZseverity�signal�sharedZslaZsllZsraZsrl�subtypeZthen�toZ	transportr{Zunitsr�r��variabler�Zwhenr�r�r�r�z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+z
X"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r�r�r�r�r�N)%r�r�r�r�r�r�r�r��re�	MULTILINE�
IGNORECASE�flagsrr	r�r
r�r
r�	Attributerrrr�rr�rrrr�rr�r�r�r�r�r�r�r�r�r�r!sp

)r�rZpygments.lexerrrrrrrZpygments.tokenrr	r
rrr
rrr�__all__rrrr�r�r�r��<module>
s ,
{